Various embodiments relate to fast-locking clock and data recovery (CDR) methods and circuits that may be used, for example, in digital communications.
To read an incoming digital data stream, it is necessary to have a clock signal that is in phase with the incoming data stream. Such a clock signal indicates to the receiving component when it should sample the incoming stream to capture the values encoded therein. This clock signal may be provided to the receiving component over a separate clock transmission channel (e.g., a wire or other conductive path, a wireless channel, etc.). According to CDR methods, however, the clock signal is derived directly from the incoming data stream, which may eliminate the need for the separate clock transmission channel.
One type of CDR circuit is a Phase Interpolation (PI) CDR circuit. In a PI CDR circuit, the clock output is generated by taking a weighted phase interpolation of two quadrature reference clock signals (i.e., clock signals separated in phase by about π/2). FIG. 1 illustrates a prior art PI CDR circuit 100. The circuit 100 comprises a phase detector 102 and a phase interpolator 104. The phase detector 102 receives an incoming data stream via preamplifier 110, and an interpolated clock signal, received from the phase interpolator 104. The outputs of the phase detector 102 include an early value and a late value. The early value is asserted if the phase of the incoming data stream is early relative to the interpolated clock signal, and the late value is asserted if the incoming data stream is late relative to the interpolated clock signal.
The phase interpolator 104 comprises a phase interpolator controller 108 and a phase interpolator core 106. The controller 108 receives the early and late values from the phase detector 102 and generates a series of phase tuning values that are provided to the core 106. The core 106 receives the tuning values, as well as the two quadrature reference clock signals, Clock I and Clock Q. The core 106 performs a phase interpolation between Clock I and Clock Q. The weighting given to the phase of each of the Clocks I and Q is determined by the tuning values. The result is the interpolated clock signal, which is provided to the phase detector 102 as described above. The interpolated clock and the incoming data stream are provided as output via an output buffer 112.
When the phase of the incoming data stream and that of the interpolated clock do not match (i.e., when either the early value or the late value is asserted), the phase interpolator 104 incrementally modifies the phase of the interpolated clock until it locks onto the phase of the incoming data stream. When the early value or the late value is asserted, the controller 108 may modify the tuning values, which in turn modifies the weighting given to Clocks I and/or Q by the core 106 and causes the phase of the interpolated clock to be incremented, or decremented, by a predetermined amount. FIG. 2 illustrates a timing plot 200 generated by the PI CDR circuit 100. The plot 200 illustrates an incoming data incoming data stream 202, an interpolated clock signal 204, Clock I, and Clock Q. The incoming data stream 202 is initially early relative to the interpolated clock. With each rising edge of the incoming data stream 202, the early value of the phase detector 102 is set, causing the controller 108 to modify the weighting given to the Clock I and Clock Q. As a result, the core 106 increments the phase of the interpolated clock toward that of the incoming data stream 202. The number of steps necessary for the interpolated clock signal 204 to lock at the phase of the incoming data stream is determined by the phase resolution of the circuit 100 and the initial phase difference between the interpolated clock signal 204 and the incoming data stream 202.